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Original research DESIGN AND DEVELOPMENT OF AN FPGA-BASED HARDWARE ACCELERATOR FOR IMPROVING COMPUTATIONAL PERFORMANCEPages 37-42
Abstract
Due to recent breakthroughs in digital technology and the accessibility of reliable data, a field of artificial intelligence called machine learning has arisen. This field has shown its capability and efficiency in addressing intricate learning issues that were previously unsolvable. Convolutional Neural Networks (CNNs) have shown to be very successful in applications involving picture identification and recognition. The demanding nature of these tasks requires substantial Central Processing Unit (CPU) processing power and storage bandwidth, which conventional CPUs cannot provide to meet the needed performance benchmarks. Therefore, hardware accelerators using Field Programmable Gate Arrays (FPGAs) have been used to enhance the efficiency of CNNs. FPGAs have been lately used to strengthen the execution of machine learning networks because of their capacity to optimize parallelism and their energy economy. This paper proposes a new composite hardware design for a CNN accelerator to tackle these difficulties. It is called a CNN-based FPGA Hardware Accelerator (CNN-FPGA-HA). The FPGA-based accelerator has clear benefits due to its programmable nature, adaptability, power efficiency, and ability to do enormous parallel processing with CNN. Based on the experimental findings, the fully pipelined CNN hardware accelerator obtains an effectiveness of 328.32 GOP/s, with a power consumption of 42.31 GOP/s/w. This indicates that CNN-FPGA-HA surpasses the outcomes of prior techniques.
Keywords: Hardware Accelerator, Convolutional Neural Network, Field Programmable Gate Arrays, Optimisation.
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Gomathi Natesan, 
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